caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1996 1 semiconductor hs-565arh radiation hardened high speed, monolithic digital-to-analog converter features ? devices qml quali?ed in accordance with mil-prf-38535 ? detailed electrical and screening requirements are contained in smd# 5962-96755 and harris qm plan ? dac and reference on a single chip ? pin compatible with ad-565a and hi-565a ? very high speed: settles to 0.50 lsb in 500ns max ? monotonicity guaranteed over temperature ? 0.50 lsb max nonlinearity guaranteed over temperature ? low gain drift (max., dac plus reference) 50ppm/ o c ? total dose hardness to 100k rad ? 0.75 lsb accuracy guaranteed over temperature ( 0.125 lsb typical at +25 o c) applications ? high speed a/d converters ? precision instrumentation ? signal reconstruction march 1996 description the hs-565arh is a fast, radiation hardened 12-bit current out- put, digital-to-analog converter. the monolithic chip includes a precision voltage reference, thin-?lm r-2r ladder, reference control ampli?er and twelve high-speed bipolar current switches. the harris semiconductor dielectric isolation process provides latch-up free operation while minimizing stray capacitance and leakage currents, to produce an excellent combination of speed and accuracy. also, ground currents are minimized to produce a low and constant current through the ground terminal, which reduces error due to code-dependent ground currents. hs-565arh die are laser trimmed for a maximum integral nonlin- earity error of 0.25 lsb at +25 o c. in addition, the low noise bur- ied zener reference is trimmed both for absolute value and mini- mum temperature coef?cient. functional diagram ref out vcc 43 + - 19.95k ref 10v 6 5 ref + - 3.5k 3k iref 0.5ma -vee pwr gnd 712 24 . . . 13 msb lsb (4x iref x code) gnd in 20v span 10v span out io dac 9.95k bip. off. 8 5k 5k 2.5k 11 10 9 ordering information part number temperature range screening level package 5962r9675501vjc -55 o c to +125 o c mil-prf-38535 level v 24 lead sbdip 5962r9675501vxc -55 o c to +125 o c mil-prf-38535 level v 24 lead ceramic flatpack HS1-565ARH (sample) +25 o c sample 24 lead sbdip hs9-565arh (sample) +25 o c sample 24 lead ceramic flatpack spec number 518795 file number 3278.2
2 hs-565arh pinouts HS1-565ARH mil-std-1835 cdip2-t24 (sbdip) top view h59-565arh mil-std-1835 cdfp4-f24 (ceramic flatpack) top view 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 nc nc vcc ref out ref gnd ref in -vee bipolar rin idac out 10v span 20v span pwr gnd bit 1 in (msb) bit 3 in bit 4 in bit 5 in bit 6 in bit 8 in bit 10 in bit 11 in bit 12 in (lsb) bit 2 in bit 7 in bit 9 in 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 1 nc nc vcc ref out ref gnd ref in -vee bipolar rin idac out 10v span 20v span pwr gnd bit 1 in bit 3 in bit 4 in bit 5 in bit 6 in bit 8 in bit 10 in bit 11 in bit 12 in bit 2 in bit 7 in bit 9 in (lsb) (msb) spec number 518795
3 speci?cations hs-565arh absolute maximum ratings thermal information vcc to power ground . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to +18v vee to power ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to -18v voltage on dac output (pin 9) . . . . . . . . . . . . . . . . . . . . -3v to +12v digital input (pins 13 - 24) to power ground . . . . . . . . . . -1v to +7v ref in to reference ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12v bipolar offset to reference ground . . . . . . . . . . . . . . . . . . . . . . . 12v 10v span r to reference ground . . . . . . . . . . . . . . . . . . . . . . . . . 12v 20v span r to reference ground . . . . . . . . . . . . . . . . . . . . . . . . . 24v junction temperature (tj) (max) . . . . . . . . . . . . . . . . . . . . . +175 o c storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 o c thermal resistance (typical) q ja ( o c/w) q jc ( o c/w) sbdip package . . . . . . . . . . . . . . . . . . 60 17 ceramic flatpack package 80 15 maximum package power dissipation at +125 o c sbdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.83w ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . . . . 0.62w if device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: sbdip package 16.67mw/ o c ceramic flatpack package 12.5mw/ o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions operating voltage range (vcc) . . . . . . . . . . . . . +11.4v to +16.5v operating voltage range (vee). . . . . . . . . . . . . . . -11.4v to -16.5v operating temperature range . . . . . . . . . . . . . . . . -55 o c to +125 o c digital input low voltage. . . . . . . . . . . . . . . . . . . . . . . . .0v to +0.8v digital input high voltage . . . . . . . . . . . . . . . . . . . . . +2.2v to +5.5v table 1. dc electrical performance characteristics parameters symbol conditions group a sub- group temperature limits units min typ max resolution vssd = vssa = 0v, vcc = +15v, vee = -15v 1, 2, 3 -55 o c to +125 o c - - 12 bits accuracy ile vssd = vssa = 0v, vcc = +15v, vee = -15v, error relative to full scale 1, 2, 3 -55 o c to +125 o c- 0.125 0.75 lsb digital input high current iih vssd = vssa = 0v, vin = 5.5v vcc = +15v, vee = -15v 1, 2, 3 -55 o c to +125 o c - 0.01 +1.0 m a digital input low current iil vssd = vssa = 0v, v in = 0v vcc = +15v, vee = -15v 1, 2, 3 -55 o c to +125 o c -20 -2.0 - m a differential nonlinearity dle vssd = vssa = 0v, vcc = +15v, vee = -15v, +25 o c (monotonicity guaranteed over temp) 1, 2, 3 -55 o c to +125 o c- 0.25 0.50 lsb power supply currents vcc icc vssd = vssa = 0v, vcc = +15v, vee = -15v 1, 2, 3 -55 o c to +125 o c - 9.0 11.8 ma vee iee vssd = vssa = 0v, vcc = +15v, vee = -15v 1, 2, 3 -55 o c to +125 o c -14.5 -9.5 - ma reference output voltage ref out vssd = vssa = 0v, vcc = +15v, vee = -15v 1, 2, 3 -55 o c to +125 o c 9.9 10 10.1 v reference output current iref vssd = vssa = 0v, vcc = +15v, vee = -15v, available for external loads 1, 2, 3 -55 o c to +125 o c 1.5 2.5 - ma output current unipolar i out1 vssd = vssa = 0v, vcc = +15v, vee = -15v, all bits on 1, 2, 3 -55 o c to +125 o c -1.6 -2.0 -2.4 ma bipolar i out2 vssd = vssa = 0v, vcc = +15v, vee = -15v, all bits on or off 1, 2, 3 -55 o c to +125 o c 0.8 1.0 1.2 ma spec number 518795
4 speci?cations hs-565arh output offset unipolar vos vssd = vssa = 0v, vcc = +15v, vee = -15v figure 3, r2 = 50 w fixed 1, 2, 3 -55 o c to +125 o c- 0.01 0.05 % of f.s. bipolar bpoe vssd = vssa = 0v, vcc = +15v, vee = -15v, r3 and r4 = 50 w fixed figure 4 1, 2, 3 -55 o c to +125 o c- 0.05 0.15 % of f.s. power supply gain sensitivity vcc +pss note 3 1, 2, 3 -55 o c to +125 o c - 3 10 ppm of f.s./% vee -pss note 3 1, 2, 3 -55 o c to +125 o c - 15 25 ppm of f.s./% temperature coef?cients unipolar zero with internal reference 1, 2, 3 -55 o c to +125 o c - 1 2 ppm/ o c bipolar zero with internal reference 1, 2, 3 -55 o c to +125 o c - 5 20 ppm/ o c gain (full scale) with internal reference 1, 2, 3 -55 o c to +125 o c - 10 50 ppm/ o c external adjustments ae fixed 50 w resistor for r2 figures 3 1, 2, 3 -55 o c to +125 o c- 0.10 0.25 % of f.s. gain error bpae fixed 50 w resistor for r3 and r4, figure 4 1, 2, 3 -55 o c to +125 o c- 0.10 0.25 % of f.s. bipolar zero error bpze fixed 50 w resistor for r3 and r4, figure 4 1, 2, 3 -55 o c to +125 o c- 0.05 0.10 % of f.s. notes: 1. all voltages referenced to vssd = vssa = 0v 2. unless otherwise specified vcc = +15v and vee = -15v. 3. the power supply gain sensitivity is tested in reference to a vcc = +15v and vee = -15v. table 2. ac electrical performance characteristics table 2 intentionally left blank. see ac speci?cations in table 3 table 3. electrical performance characteristics parameters symbol conditions notes temperature limits units min typ max output capacitance cout f = 1mhz 1, 2 +25 o c - 20 - pf output compliance voltage 1 -55 o c to +125 o c -1.5 - 10 v programmable output ranges 1 -55 o c to +125 o c0 - 5 v 1 -55 o c to +125 o c -2.5 - 2.5 v 1 -55 o c to +125 o c0 - 10 v 1 -55 o c to +125 o c-5 - 5 v 1 -55 o c to +125 o c -10 - 10 v gain adjustment range figures 3, 4 1 -55 o c to +125 o c 0.25 - - % of f.s. bipolar zero adjustment range figure 4 1 -55 o c to +125 o c 0.15 - - % of f.s. reference input impedance rref vssd = vssa = 0v, -15 vcc = +15v, vee = -15v 1 -55 o c to +125 o c 15k 20k 25k w output resistance rout vssd = vssa = 0v, vcc = +15v, vee = -15v, exclusive of span resistors 1 -55 o c to +125 o c 1.8k 2.5k 3.2k w table 1. dc electrical performance characteristics (continued) parameters symbol conditions group a sub- group temperature limits units min typ max spec number 518795
5 speci?cations hs-565arh settling time (note 3) ts1 vssd = vssa = 0v, vcc = +15v, vee = -15v, high z external load 1 -55 o c to +125 o c - 350 500 ns ts2 vssd = vssa = 0v, vcc = +15v, vee = -15v, 75 w external load 1 -55 o c to +125 o c - 150 250 ns full scale transition rise time trise vssd = vssa = 0v, vcc = +15v, vee = -15v 1 -55 o c to +125 o c - 15 30 ns fall time tfall vssd = vssa = 0v, vcc = +15v, vee = -15v 1 -55 o c to +125 o c - 30 60 ns notes: 1. the parameters listed in table 3 are controlled via design or process and are not tested. these parameters are characterized upon initial design release. 2. 24 lead dip package only. 3. reference the settling time discussion and figure 3. table 4. post 100 k rad electrical performance post 100k rad electrical performance is per table 1 (+25 o c only) except as follows: parameter symbol conditions: +25 o c only limits units min max digital inputs low current i il v in = 0.0v -40 - m a low voltage v il (note 1) - 0.5 v high voltage v ih (note 1) 2.5 - v unipolar full scale error ae figure 3, r2 = 50 w fixed - 0.85 % of f.s. bipolar offset error bpoe figure 4, r3 and r4 = 50 w fixed - 0.25 % of f.s zero error bpze figure 5, r3 and r4 = 50 w fixed - 0.25 % of f.s. full scale error bpae figure 5, r3 and r4 = 50 w fixed - 0.85 % of f.s. differential nonlinearity dle monotonicity guaranteed - 1.0 lsb accuracy ile error relative to full scale - 1.0 lsb notes: 1. this parameter is an applied condition of test. table 5. bi delta parameters ( 25 o c) parameter delta limit i cc 1.18ma i ee 1.45ma i out1 240 m a i out2 240 m a vos 0.02% ae 0.15% bpoe 0.10% bpze 0.10% i il 1.0 m a i ih 40na table 3. electrical performance characteristics (continued) parameters symbol conditions notes temperature limits units min typ max spec number 518795
6 speci?cations hs-565arh spec number 518795 burn-in bias circuit radiation bias circuit notes: d1 = d2 = d3 = in4002 or equivalent f0 to f11: vih = 5.0v 0.5v vil = 0.0v 0.5v f0 = 100khz 10% (50% duty cycle) f1 = f0/2 f7 = f0/128 f2 = f0/4 f8 = f0/256 f3 = f0/8 f9 = f0/512 f4 = f0/16 f10 = f0/1024 f5 = f0/32 f11 = f0/2048 f6 = f0/64 note: power supply levels are 0.5v c3 d3 +10v 1 4 5 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 2 3 6 7 nc c1 d1 +15v c2 d2 -15v f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 nc vcc ref gnd ref out ref in -vee bip off out 10v span 20v span pwr gnd bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 +15v 1 4 5 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 2 3 6 7 nc nc vcc ref gnd ref out ref in -vee bip off out 10v span 20v span pwr gnd bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 -15v +10v +5v de?nitions of speci?cations digital inputs the hs-565arh accepts digital input codes in binary format and may be user connected for any one of three binary codes. straight binary, twos complement (see note below), or offset binary, (see operating instructions). accuracy nonlinearity - nonlinearity of a d/a converter is an impor- tant measure of its accuracy. it describes the deviation from an ideal straight line transfer curve drawn between zero (all bits off) and full scale (all bits on). differential nonlinearity - for a d/a converter, it is the difference between the actual output voltage change and the digital input analog output straight binary offset binary (note) twos complement msb . lsb 000 . . .000 zero -fs (full scale) zero 100 . . .000 0.50 fs zero -fs 111 . . .111 +fs - 1lsb +fs - 1lsb zero - 1lsb 011 . . .111 0.50 fs - 1lsb zero - 1lsb +fs - 1lsb note: invert msb with external inverter to obtain twos complement coding ideal (1 lsb) voltage change for a one bit change in code. a differential nonlinearity of 1 lsb or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. settling time settling time is the time required for the output to settle to within the speci?ed error band for any input code transition. it is usually speci?ed for a full scale or major carry transition, settling to within 0.50 lsb of ?nal value. drift gain drift - the change in full scale analog output over the speci?ed temperature range expressed in parts per million of full scale range per o c (ppm of fsr/ o c). gain error is measured with respect to +25 o c at high (th) and low (tl) temperatures. gain drift is calculated for both high (th - 25 o c) and low ranges (+25 o c - tl) by dividing the gain error by the respective change in temperature. the speci?cation is the larger of the two representing worst case drift. offset drift - the change in analog output with all bits off over the speci?ed temperature range expressed in parts per million of full scale range per o c (ppm of fsr/ o c). offset error is measured with respect to +25 o c at high (th) and low (tl) temperatures. offset drift is calculated for both high (th - 25 o c) and low (+25 o c - tl) ranges by dividing the offset error by the
7 hs-565arh respective change in temperature. the speci?cation given is the larger of the two, representing worst case drift. power supply sensitivity power supply sensitivity is a measure of the change in gain and offset of the d/a converter resulting from a change in -15v or +15v supplies. it is speci?ed under dc conditions and expressed as parts per million of full scale range per percent of change in power supply (ppm of fsr/%). compliance compliance voltage is the maximum output voltage range that can be tolerated and still maintain its speci?ed accuracy. compliance limit implies functional operation only and makes no claims to accuracy. glitch a glitch on the output of a d/a converter is a transient spike resulting from unequal internal on-off switching times. worst case glitches usually occur at half scale or the major carry code transition from 011 . . . 1 to 100 . . . 0 or vice versa. for example, if turn on is greater than turn off for 011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0 exists, such that, the output momentarily glitches toward zero output. matched switching times and fast switching will reduce glitches considerably. applying the hs-565arh op amp selection the hs-565arhs current output may be converted to voltage using the standard connections shown in figures 3 and 4. the choice of operational ampli?er should be reviewed for each application, since a signi?cant trade-off may be made between speed and accuracy. remember settling time for the dac-ampli?er combination is where t d , t a are settling times for the dac and ampli?er. figure 3. unipolar voltage output no trim operation the hs-565arh will perform as speci?ed without calibration adjustments. to operate without calibration, substitute 50 w resistors for the 100 w trimming potentiometers: in figure 3 replace r2 with 50 w ; also remove the network on pin 8 and connect 50 w to ground. for bipolar operation in figure 4, replace r3 and r4 with 50 w resistors. with these changes, performance is guaranteed as shown under speci?cations, external adjustments. typical unipolar zero will be 0.50 lsb plus the op amp offset. the feedback capacitor c must be selected to minimize settling time. figure 4. bipolar voltage output calibration calibration provides the maximum accuracy from a converter by adjusting its gain and offset errors to zero, for the hs-565arh, these adjustments are similar whether the current output is used, or whether an external op amp is added to convert this current to a voltage. refer to table 7 for the voltage output case, along with figure 3 or 4. calibration is a two step process for each of the ?ve output ranges shown in table 7. first adjust the negative full scale (zero for unipolar ranges). this is an offset adjust which translates the output characteristic, i.e. affects each code by the same amount. next adjust positive fs. this is a gain error adjustment, which rotates the output characteristic about the negative fs value. for the bipolar ranges, this approach leaves an error at the zero code, whose maximum values is the same as for integral nonlinearity error. in general, only two values of output may be calibrated exactly; all others must tolerate some error. choosing the extreme end points (plus and minus full scale) minimizes this distributed error for all other codes. t d () 2 t a () 2 + vo - + r (see table 7) dac out 9 10 11 20v span 10v span 2.5k 5k 5k c 9.95k io 24 13 msb lsb . . . . . code input dac (4 x iref -vee pwr gnd 7 x code) iref 0.5ma hs-565arh 3k 3.5k 19.95 k + - 10v 3 4 vcc + - 6 5 ref gnd ref in ref out r2 100 w 8 bip. off. +15v -15v r1 50k w 100k w 100 w vo - + r (see table 7) dac out 9 10 11 20v span 10v span 2.5k 5k 5k c 9.95k io 24 13 msb lsb . . . . . code input dac (4 x iref -vee pwr gnd 7 x code) iref 0.5ma hs-565arh 3k 3.5k 19.95k + - 10v 3 4 vcc + - 6 5 ref gnd ref in ref out r4 100 w 8 bip. off. r3 100 w spec number 518795
8 hs-565arh settling time this is a challenging measurement, in which the result depends on the method chosen, the precision and quality of test equipment and the operating con?guration of the dac (test conditions). as a result, the different techniques in use by converter manufacturers can lead to consistently different results. an engineer should understand the advantage and limitations of a given test methods before using the speci?ed settling time as a basis for design. the approach used for several years at harris calls for a strobed comparator to sense ?nal perturbations of the dac output waveform. this gives the lsb a reasonable magnitude (814mv for the hs-565arh, which provides the comparator with enough overdrive to establish an accurate 0.50 lsb window about the ?nal settled value. also, the required test conditions simulate the dacs environment for a common application - use in a successive approximation a/ d converter. considerable experience has shown this to be a reliable and repeatable way to measure settling time. the usual speci?cation is based on a 10v step, produced by simultaneously switching all bits from off-to-on (ton) or on-to-off (toff). the slower of the two cases is speci?ed, as measured from 50% of the digital input transition to the ?nal entry within a window of 0.50 lsb about the settled value. four measurements characterize a given type of dac: (a) ton, to final value +0.50 lsb (b) ton, to final value -0.50 lsb (c) toff, to final value +0.50 lsb (d) off, to final value -0.50 lsb (cases (b) and (c) may be eliminated unless the overshoot exceeds 0.50 lsb). for example, refer to figures 5a and5b for the measurement of case (d). procedure as shown in figure 5b, settling time equals tx plus the comparator delay (td = 15ns). to measure tx, ? adjust the delay on generator number 2 for a tx of several microseconds. this assures that the dac output has settled to its ?nal wave. ? switch on the lsb (+5v) ? adjust the vlsb supply for 50% triggering at compara- tor out. this is indicated by traces of equal brightness on the oscilloscope display as shown in figure 5b. note dvm reading. ? switch to lsb to pulse (p) ? readjust the vlsb supply for 50% triggering as before, and note dvm reading. one lsb equals one tenth the difference in the dvm readings noted above. ? adjust the vlsb supply to reduce the dvm reading by 5 lsbs (dvm reads 10x, so this sets the comparator to sense the ?nal settled value minus 0.50 lsb). com- parator output disappears. ? reduce generator number 2 delay until comparator output reappears, and adjust for equal brightness. ? measure tx from scope as shown in figure 5b. settling time equals tx + td, i.e. tx + 15ns. table 7. operating modes and calibration mode circuit connections calibration output range pin 10 to pin 11 to resistor (r) apply input code adjust to set vo unipolar (see figure 3) 0 to +10v vo pin 10 1.43k all 0s all 1s r1 r2 0v +9.99756v 0 to +5v vo pin 9 1.1k all 0s all 1s r1 r2 0v +4.99878v bipolar (see figure 4) 10v nc vo 1.69k all 0s all 1s r3 r4 -10v +9.99512v 5v vo pin 10 1.43k all 0s all 1s r3 r4 -5v +4.99756v 2.5v vo pin 9 1.1k all 0s all 1s r3 r4 -2.5v +2.49878v spec number 518795
9 hs-565arh figure 5a. figure 5b. vlsb supply 0.1 m f dvm comparator out b c 10 90 200k + - 5 9 10 nc 11 8 2.5k 5k 5k 20v 20% bias turn on turn off 9.95k 2ma 12 hs-565arh d pulse generator no. 2 out 14 13 23 24 . . . . . . . . . . . . . 5v p pulse generator no. 1 sync in trig out out a ~100 khz strobe in lsb 50% digital input dac output comp. strobe comp. out equal brightness +3v 0v 0v -400mv 2v 0.8v 4v 0v (turn off) a b c d 50% tx td = comparator delay settling time -0.50lsb spec number 518795 other considerations grounds the hs-565arh has two ground terminals, pin 5 (ref gnd) and pin 12 (pwr gnd). these should not be tied together near the package unless that point is also the system signal ground to which all returns are connected. (if such a point exists, then separate paths are required to pins 5 and 12). the current through pin 5 is near zero dc (note); but pin 12 carries up to 1.75ma of code - dependent current from bits 1, 2, and 3. the general rule is to connect pin 5 directly to the system quiet point, usually called signal or analog ground. connect pin 12 to the local digital or power ground. then, of course, a single path must connect the analog/ signal and digital/power grounds. note: current cancellation is a two step process within the hs- 565arh in which code dependent variations are eliminated, the resulting dc current is supplied internally. first an auxiliary 9-bit r-2r ladder is driven by the complement of the dacs input code. together, the main and auxiliary ladders draw a continuous 2.25ma from the internal ground node, re- gardless of input code. part of the dc current is supplied by the zener voltage reference, and the remainder is sourced from the positive supply via a current mirror which is laser trimmed for zero current through the external terminal (pin 5). layout connections to pin 9 (iout) on the hs-565arh are most crit- ical for high speed performance. output capacitance of the dac is only 20pf, so a small change of additional capacitance may alter the op amps stability and affect settling time. con- nections to pin 9 should be short and few. component leads should be short on the side connecting to pin 9 (as for feed- back capacitor c). see the settling time section. bypass capacitors power supply bypass capacitors on the op amp will serve the hs-565arh also. if no op amp is used, a 0.01 m f ceramic capacitor from each supply terminal to pin 12 is suf?cient, since supply current variations are small. die characteristics transistor count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 die size . . . . . . . . . . . . . . . . . . . . . . . . . 179 mils x 107 mils tie substrate to . . . . . . . . . . . . . . . . . . . .reference ground process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bipolar - di
10 hs-565arh metallization mask layout hs-565arh die characteristics die dimensions: 179 mils x 107 mils x 19 mils metallization: type: al/copper thickness: 16k ? 2k ? glassivation: type: sio 2 thickness: 8k ? 1k ? worst case current density: 2.0 x 10 5 a/cm 2 vcc (msb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 (lsb) power gnd 20v span 10v span idac out bipolar 12 -vs vref in vref gnd vref out 3 nc 3 nc 1 a spec number 518795
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